Field notes
ISA extensions, compiler internals, AI infrastructure — the layers between a model and the silicon it runs on. We write about them because we work on them.
Becoming the Human in the Loop
AI-assisted engineering changes who wins in deep tech — and it's not who most people think. The throughput gains are real, but only when architect-level engineers are steering. Speed without judgement is an unguided missile.
Makeljana Shkurti
Now Comes the Hard Part.
A compelling architecture and a production-ready platform are two entirely different things. The distance between them is where most of the honest work still needs to happen.
Makeljana Shkurti
And what the Zicond ISA extension does about it
A missing instruction in RISC‑V created a class of problems where branch direction determines register allocation quality. Two instructions eliminate the entire problem.
Philipp Tomsich
RISC‑V Summit North America 2025
Edge AI needs an architecture that is open, modular, and built to evolve. At RISC‑V Summit NA 2025, we once again made the case that RISC‑V is that architecture — and that the opportunity is now.
Makeljana Shkurti
The Economics of Building on an Open Architecture
The architecture decision at the heart of every AI chip. Why RISC‑V wins on economics, customisation, and the ability to evolve with software-defined workloads — and what the standards process has to do with it.
Makeljana Shkurti
The 1st Sino-European Workshop on Computer Architecture R&D and RISC‑V
When researchers building RISC‑V in Beijing and Basel are solving the same problems, what happens when you put them in the same room? Three days in Tirana gave us the answer.
Makeljana Shkurti