What we ship
From ISA to inference. One team.
Processors become platforms only when compilers, runtimes, and ecosystems exist around them. The software performance we've delivered for production ARM silicon is the foundation we're building on for the RISC-V architectures shaping the next decade of AI.
01
Strategic R&D & ISA Design
We find the instructions your silicon is missing.
We run AI workloads against production silicon until the ISA breaks — then design the extensions that fix it. Matrix-computing instructions. Inference primitives. The operations your application-specific silicon needs before it can ship. We do this inside the RISC‑V standards process, not outside it — because an extension that isn't upstream is an extension your customers can't rely on. Most ISA proposals stall because they were designed without compiler or workload context. Ours don't.
In practice
- Benchmark & workload intelligence
- Microarchitectural design exploration
- ISA extension definition (e.g. matrix-computing extensions for AI)
- Pre-silicon functional simulation
- Performance prediction & competitive analysis
- Application-defined instruction optimization
02
Compiler & Performance Engineering
Hardware performance is a compiler problem.
We've spent years inside production compilers finding where AI workloads stall — vectorisation limits, MLIR graphs that never reach the hardware. Those scars are now RISC‑V advantages: MLIR pipelines, RVV and matrix extension backends, and code generation that makes custom ISA extensions worth the silicon. We work in both GCC and LLVM — not as a preference, but because your customers use both and neither can be an afterthought. From intrinsics design through auto-vectorisation to application-level profiling, we close the gap between what the hardware can do and what the software actually does.
In practice
- GCC & LLVM development
- MLIR-based compilation pipelines for AI
- Vectorization & SIMD optimization (RVV, SVE, SME)
- Code generation for custom ISA extensions
- Performance analysis & profiling
- Application tuning & intrinsics development
- Runtime & library optimization
03
Software Ecosystem Enablement
Silicon becomes a platform when developers can build on it.
We've shipped PyTorch, TensorFlow, and ONNX Runtime on production silicon. We know what "ready" means — and how far most platforms are from it. We bring that standard to RISC‑V: framework bring-up, inference runtime optimisation, and the upstream work that gets developers building. Porting a framework is the easy part. Making it pass conformance, hit competitive performance, and stay upstream across release cycles — that's where most enablement efforts die. We maintain what we ship.
In practice
- SDK development & integration
- Upstream open-source enablement (Linux, DPDK, GNU toolchain, LLVM)
- Platform bring-up & board support
- AI framework porting & optimization (PyTorch, TensorFlow, ONNX Runtime)
- Inference runtime tuning
- Conformance & compliance testing (RVA profiles)
- Developer tooling & documentation
Real projects. Every layer.
RISC‑V matrix extensions.
From spec to upstream.
Standardizing matrix-computing for RISC‑V — reducing fragmentation, building on ecosystem efforts, and defining interoperability across AI-accelerated silicon.
Strategic R&D
Profiled AI workloads, defined the extension spec
Compilers
Built code-gen and auto-vectorization in GCC & LLVM
Ecosystem
Upstreamed to GCC/LLVM, wired into PyTorch
Strategic R&D
Profiled AI workloads, defined the extension spec
Compilers
Built code-gen and auto-vectorization in GCC & LLVM
Ecosystem
Upstreamed to GCC/LLVM, wired into PyTorch
RISC‑V SmartNIC.
AI networking at wire speed.
Scale-out networking for AI clusters — wire-speed packet processing on RISC‑V silicon that replaces proprietary NICs.
Strategic R&D
Benchmarked packet-processing pipelines, identified crypto and CRC bottlenecks
Compilers
CRC & crypto intrinsics, Zvbc vectorized
Ecosystem
DPDK backend from scratch, RVA23 certified
Strategic R&D
Benchmarked packet-processing pipelines, identified crypto and CRC bottlenecks
Compilers
CRC & crypto intrinsics, Zvbc vectorized
Ecosystem
DPDK backend from scratch, RVA23 certified
Embedded RISC‑V.
Inference on 2W silicon.
On-device AI at the power envelope of a sensor — production inference on microcontroller-class RISC‑V.
Strategic R&D
Designed custom instructions for the target workload
Compilers
Code-gen for custom ops, hand-tuned kernels
Ecosystem
Ported inference framework, shipped the SDK
Strategic R&D
Designed custom instructions for the target workload
Compilers
Code-gen for custom ops, hand-tuned kernels
Ecosystem
Ported inference framework, shipped the SDK